sampling clock中文是什么意思

發(fā)音:

中文翻譯
造句

取樣鐘

sampling n. 1.取樣(品)，取標(biāo)(本)〔指行動(dòng)或程序〕。 2. ...
clock n. 襪子跟部[側(cè)面下方]的織繡花紋。 vt. 織[繡] ...
sampling clock noise 采樣時(shí)鐘帶來(lái)的噪聲; 采樣時(shí)鐘噪聲
a clock 一個(gè)鬧鐘
clock n. 1.鐘；掛鐘，座鐘，上下班計(jì)時(shí)計(jì)。 2.〔俚語(yǔ)〕記秒表，卡馬表；〔美俚〕〔pl.〕駕駛儀表，速度表，里程計(jì)。 3.〔英俚〕(人的)面孔。 4.〔the C-〕【天文學(xué)】時(shí)鐘座〔星座名〕。 5.【自動(dòng)化】(電子計(jì)算機(jī)的)時(shí)鐘脈沖(器)。 a Dutch clock(報(bào)時(shí)發(fā)杜鵑鳴聲的)杜鵑鐘 (＝cuckoo-clock)。 an eight-day clock八日上一次發(fā)條的鐘。 a musical clock八音鐘。 the face of a clock鐘的字碼盤。 What of the clock 〔古謔〕＝ What o'clock is it 現(xiàn)在是幾點(diǎn)鐘？ wind up the clock上(鐘的)發(fā)條。 around the clock ＝ round the clock. clock calm 海面平靜如鏡。 fight the clock 搶時(shí)間。 like a clock 鐘表似地，準(zhǔn)確地，按部就班地。 put [set, turn] back the clock 把鐘撥慢，倒撥；〔比喻〕阻礙進(jìn)步；復(fù)古；開倒車；隱瞞年齡；扭轉(zhuǎn)歷史車輪。 race the clock 爭(zhēng)分奪秒。 regulate [set] a clock by …根據(jù)…對(duì)鐘。 round the clock ＝the clock round 晝夜不停，連續(xù)一整天。 set ahead a clock 把鐘撥快。 when one's clock strikes 臨終。 work against the clock 搶時(shí)間做完。 vt. 1.為(比賽等)計(jì)時(shí)；(運(yùn)動(dòng)員等)用…時(shí)間跑[游]完。 2.(用機(jī)械)記錄(速度、距離、次數(shù)等)。 clock a swimmer (用跑表)記錄游泳選手的成績(jī)。 clock five minutes for the whole distance 用5分鐘跑[游]完全程。 vi. (在自動(dòng)計(jì)時(shí)器上)記下考勤。 clock in [out] ＝clock on [off] (用鐘鈴裝置自動(dòng))鳴報(bào)開始[終止]時(shí)間；(職工用自動(dòng)記錄時(shí)鐘)記錄上班[下班]時(shí)間。 clock in (an hour) at (the work) 花(一小時(shí))在(工作上)。 n. -er (比賽等的)計(jì)時(shí)員；交通量計(jì)算員。 n. 襪子跟部[側(cè)面下方]的織繡花紋。 vt. 織[繡]上襪跟部[側(cè)下方]花紋。
clock in 打卡上班; 記錄上班時(shí)間; 時(shí)鐘脈沖輸入; 時(shí)鐘輸入
clock on 打卡上班; 記錄上班時(shí)間
clock-on 鎖定
the clock 鬧鐘; 時(shí)鐘
sampling n. 1.取樣(品)，取標(biāo)(本)〔指行動(dòng)或程序〕。 2.樣品，標(biāo)本。 3. 剽竊拼湊歌曲。
clock cycle clock rate 時(shí)鐘周期時(shí)鐘頻率
clock offset，clock correction 鐘差
pendule (clock); pendulum clock 擺鐘
secondary clock; slave clock 子鐘
simulated clock simulation clock 模擬時(shí)鐘
striking clock; chime clock 自鳴鐘
table clock; bracket clock 臺(tái)鐘
table clock; desk clock 座鐘
a clock watcher 老是看鐘表等下班的人; 舞會(huì)上無(wú)人邀請(qǐng)的女子
a desk clock 一具座鐘
about clock 關(guān)于時(shí)鐘
absolute clock 絕對(duì)時(shí)鐘
after clock 時(shí)鐘后
against the clock 分秒必爭(zhēng); 運(yùn)動(dòng)員單獨(dú)比賽單獨(dú)計(jì)時(shí)的比賽方法
airborne clock 空用時(shí)鐘

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例句與用法

Of course the sampling clock is itself a digital signal
時(shí)鐘本身也是數(shù)字信號(hào)，也會(huì)干擾模擬電路。
The sampling clock generator must also have adequate spectral purity
時(shí)鐘發(fā)生電路固有的抖動(dòng)應(yīng)該足夠小。
Figure 5 . 36 shows the relationship between sampling clock jitter and snr previously presented
圖5 . 36顯示了采樣時(shí)鐘抖動(dòng)和信噪比之間的關(guān)系。
To achieve this the sampling clock should be isolated as much as possible from the noise present in the digital parts of the system
為此，時(shí)鐘信號(hào)應(yīng)該盡可能地與電路中強(qiáng)噪聲的部分隔離開，例如數(shù)字電路。
The adc aperture jitter must be minimal , and the sampling clock generated from a low phase - noise quartz crystal oscillator
Adc的孔徑抖動(dòng)必需盡可能的小，而且要使用低相位噪聲的石英晶體振蕩器作為采樣時(shí)鐘發(fā)生器。
The ep2s15 of altera company , work as the system ’ s peripheral controller include fifo ( first in first out ) memory and sampling clock controller
Altera公司的ep2s15作為系統(tǒng)的外圍控制器,實(shí)現(xiàn)對(duì)系統(tǒng)的fifo (先進(jìn)先出存儲(chǔ)器)與采樣時(shí)鐘的控制。
In this paper design of some circuit including in a / d circuit is also analyzed , such as front analog circuit , sample clock circuit and data flip - latch circuit
同時(shí)對(duì)高速轉(zhuǎn)換器件及轉(zhuǎn)換電路中包括前端模擬電路、采樣時(shí)鐘、后端數(shù)據(jù)鎖存等輔助電路設(shè)計(jì)進(jìn)行了分析。
As to phased array receiving , a scheme of separating the delay clock and sampling clock is explicated , which effectively enhance the phased receiving delay resolution
對(duì)于相控接收延時(shí)，本文闡述了一種將延時(shí)時(shí)鐘和采樣時(shí)鐘分離的方案，有效地提高了接收延時(shí)分辨率。
Those include power supply circuit design ; ground plane design and sample clock design . combining some radar development , its high - speed a / d circuit is tested , and has given out some test results
最后結(jié)合某雷達(dá)研制，對(duì)其高速模數(shù)轉(zhuǎn)換電路設(shè)計(jì)進(jìn)行了實(shí)際測(cè)試評(píng)估，并給出了部分測(cè)試結(jié)果。
Such as harmonic distorted in front analog circuit , sample clock shaking , analog power and the noise in ground plane etc . some suggestion of circuit design is given to improve high - speed a / d circuit performance
在高速模數(shù)轉(zhuǎn)換電路的應(yīng)用設(shè)計(jì)中地電源供電設(shè)計(jì)、模數(shù)地平面設(shè)計(jì)、采樣時(shí)鐘設(shè)計(jì)等方面提出一些具有指導(dǎo)性的意見。

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